This application was orginally filed with Code Listings 1-35 which are now included in a computer program listing appendix. This appendix includes a total 203 frames of microfiche which are placed on a compact disc.
1. Field of the Invention
This invention relates to receivers of electromagnetic signals employing multicarrier modulation. More particularly this invention relates to a digital receiver which is implemented on a single VLSI chip for receiving transmissions employing orthogonal frequency division multiplexing, and which is suitable for the reception of digital video broadcasts.
2. Description of the Related Art
Coded orthogonal frequency division multiplexing (xe2x80x9cCOFDMxe2x80x9d) has been proposed for digital audio and digital video broadcasting, both of which require efficient use of limited bandwidth, and a method of transmission which is reliable in the face of several effects. For example the impulse response of a typical channel can be modeled as the sum of a plurality of Dirac pulses having different delays. Each pulse is subject to a multiplication factor, in which the amplitude generally follows a Rayleigh law. Such a pulse train can extend over several microseconds, making unencoded transmission at high bit rates unreliable. In addition to random noise, impulse noise, and fading, other major difficulties in digital terrestrial transmissions at high data rates include multipath propagation, and adjacent channel interference, where the nearby frequencies have highly correlated signal variations. COFDM is particularly suitable for these applications. In practical COFDM arrangements, relatively small amounts of data are modulated onto each of a large number of carriers that are closely spaced in frequency. The duration of a data symbol is increased in the same ratio as the number of carriers or subchannels, so that inter-symbol interference is markedly reduced.
Multiplexing according to COFDM is illustrated in FIGS. 1 and 2, wherein the spectrum of a single COFDM carrier or subchannel is indicated by line 2. A set of carrier frequencies is indicated by the superimposed waveforms in FIG. 2, where orthogonality conditions are satisfied. In general two real-valued functions are orthogonal if                                           ∫            a            b                    ⁢                                                    ψ                p                            ⁡                              (                t                )                                      ⁢                                          ψ                q                *                            ⁡                              (                t                )                                      ⁢                          xe2x80x83                        ⁢                          ⅆ              t                                      =        K                            (        1        )            
where K is a constant, and K=0 if pxe2x89xa0q; Kxe2x89xa00 if p=q. Practical encoding and decoding of signals according to COFDM relies heavily on the fast Fourier transform (xe2x80x9cFFTxe2x80x9d), as can be appreciated from the following equations.
The signal of a carrier c is given by
sc(t)=Ac(t)ej[xcfx89ct+xcfx86c(t)]xe2x80x83xe2x80x83(2) 
where Ac is the data at time t, xcfx89c is the frequency of the carrier, and xcfx86c is the phase. N carriers in the COFDM signal is given by                                           s            s                    ⁡                      (            t            )                          =                              (                          1              /              N                        )                    ⁢                                    ∑                              n                =                0                            N                        ⁢                                                            A                  n                                ⁡                                  (                  t                  )                                            ⁢                              ⅇ                                  j                  ⁡                                      [                                                                                            ω                          n                                                ⁢                        t                                            +                                                                        φ                          n                                                ⁡                                                  (                          t                          )                                                                                      ]                                                                                                          (        3        )            
xcfx89n=xcfx890+nxcex94xcfx89xe2x80x83xe2x80x83(4) 
Sampling over one symbol period, then
xcfx86c(t)xcfx86nxe2x80x83xe2x80x83(5) 
Ac(t)Anxe2x80x83xe2x80x83(6) 
With a sampling frequency of 1/T, the resulting signal is represented by                                           s            s                    ⁡                      (            t            )                          =                              (                          1              /              N                        )                    ⁢                                    ∑                              n                =                0                            N                        ⁢                                                            A                  n                                ⁡                                  (                  t                  )                                            ⁢                              ⅇ                                  j                  ⁡                                      [                                                                                            (                                                                                    ω                              n                                                        +                                                          n                              ⁢                                                              xe2x80x83                                                            ⁢                              Δ                              ⁢                                                              xe2x80x83                                                            ⁢                              ω                                                                                )                                                ⁢                        kT                                            +                                              φ                        n                                                              ]                                                                                                          (        7        )            
Sampling over the period of one data symbol T=NT, with xcfx890=0,                                           s            s                    ⁡                      (            kT            )                          =                              (                          1              /              N                        )                    ⁢                                    ∑                              n                =                0                                            N                -                1                                      ⁢                                          A                n                            ⁢                              ⅇ                                  j                  ⁢                                      xe2x80x83                                    ⁢                                      φ                    n                                                              ⁢                              ⅇ                                                      j                    ⁡                                          (                                              n                        ⁢                                                  xe2x80x83                                                ⁢                        Δ                        ⁢                                                  xe2x80x83                                                ⁢                        ω                                            )                                                        ⁢                  kT                                                                                        (        8        )            
which compares with the general form of the inverse discrete Fourier transform:                               g          ⁡                      (            kT            )                          =                              (                          1              /              N                        )                    ⁢                                    ∑                              n                =                0                                            N                -                1                                      ⁢                                          G                ⁡                                  (                                      n                    /                                          (                      kT                      )                                                        )                                            ⁢                              ⅇ                                  jπ                  ⁢                                      xe2x80x83                                    ⁢                                      n                    ⁡                                          (                                              k                        /                        N                                            )                                                                                                                              (        9        )            
In the above equations Anejxcfx86n is the input signal in the sampled frequency domain, and Ss(kT) is the time domain representation. It is known that increasing the size of the FFT provides longer symbol durations and improves ruggedness of the system as regards echoes which exceed the length of the guard interval. However computational complexity increases according to Nlog2N, and is a practical limitation.
In the presence of intersymbol interference caused by the transmission channel, orthogonality between the signals is not maintained. One approach to this problem has been to deliberately sacrifice some of the emitted energy by preceding each symbol in the time domain by an interval which exceeds the memory of the channel, and any multipath delay. The xe2x80x9cguard intervalxe2x80x9d so chosen is large enough to absorb any intersymbol interference, and is established by preceding each symbol by a replication of a portion of itself. The replication is typically a cyclic extension of the terminal portion of the symbol. Referring to FIG. 3, a data symbol 4 has an active interval 6 which contains all the data transmitted in the symbol. The terminal portion 8 of the active interval 6 is repeated at the beginning of the symbol as the guard interval 10. The COFDM signal is represented by the solid line 12. It is possible to cyclically repeat the initial portion of the active interval 6 at the end of the symbol.
Transmission of COFDM data can be accomplished according to the known general scheme shown in FIG. 4. A serial data stream 14 is converted to a series of 15 parallel streams 16 in a serial-to-parallel converter 18. Each of the parallel streams 16 is grouped into x bits each to form a complex number, where x determines the signal constellation of its associated parallel stream. After outer coding and interleaving in block 20 pilot carriers are inserted via a signal mapper 22 for use in synchronization and channel estimation in the receiver. The pilot carriers are typically of two types. Continual pilot carriers are transmitted in the same location in each symbol, with the same phase and amplitude. In the receiver, these are utilized for phase noise cancellation, automatic frequency control, and time/sampling synchronization. Scattered pilot carriers are distributed throughout the symbol, and their location typically changes from symbol to symbol. They are primarily useful in channel estimation. Next the complex numbers are modulated at baseband by the inverse fast Fourier transform (xe2x80x9cIFFTxe2x80x9d) in block 24. A guard interval is then inserted at block 26. The discrete symbols are then converted to analog, typically low-pass filtered, and then upconverted to radiofrequency in block 28. The signal is then transmitted through a channel 30 and received in a receiver 32. As is well known in the art, the receiver applies an inverse of the transmission process to obtain the transmitted information. In particular an FFT is applied to demodulate the signal.
A modern application of COFDM has been proposed in the European Telecommunications Standard ETS 300 744 (March 1997), which specifies the framing structure, channel coding, and modulation for digital terrestrial television. The specification was designed to accommodate digital terrestrial television within the existing spectrum allocation for analog transmissions, yet provide adequate protection against high levels of co-channel interference and adjacent channel interference. A flexible guard interval is specified, so that the system can support diverse network configurations, while maintaining high spectral efficiency, and sufficient protection against co-channel interference and adjacent channel interference from existing PAL/SECAM services. The noted European Telecommunications Standard defines two modes of operation. A xe2x80x9c2K modexe2x80x9d, suitable for single transmitter operation and for small single frequency networks with limited transmitter distances. An xe2x80x9c8K modexe2x80x9d can be used for either single transmitter operation or for large single frequency networks. Various levels of quadrature amplitude modulation (xe2x80x9cQAMxe2x80x9d) are supported, as are different inner code rates, in order to balance bit rate against ruggedness. The system is intended to accommodate a transport layer according to the Moving Picture Experts Group (xe2x80x9cMPEGxe2x80x9d), and is directly compatible with MPEG-2 coded TV signals (ISO/IEC 13818).
In the noted European Telecommunications Standard data carriers in a COFDM frame can be either quadrature phase shift keyed (xe2x80x9cQPSKxe2x80x9d), 16-QAM, 64-QAM, non-uniform 16-QAM, or non-uniform 64-QAM using Gray mapping.
An important problem in the reception of COFDM transmission is difficulty in maintaining synchronization due to phase noise and jitter which arise from upconversion prior to transmission, downconversion in the receiver, and the front end oscillator in the tuner, which is typically a voltage controlled oscillator. Except for provision of pilot carriers to aid in synchronization during demodulation, these issues are not specifically addressed in the noted European Telecommunications Standard, but are left for the implementer to solve.
Basically phase disturbances are of two types. First, noisy components which disturb neighbor carriers in a multicarrier system are called the xe2x80x9cforeign noise contributionxe2x80x9d (xe2x80x9cFNCxe2x80x9d). Second, a noisy component which disturbs its own carrier is referred to as the xe2x80x9cown noise contributionxe2x80x9d.
Referring to FIG. 5, the position of ideal constellation samples are indicated by xe2x80x9cxxe2x80x9d symbols 34. The effect of foreign noise contribution is stochastic, resulting in Gaussian-like noise. Samples perturbed in this manner are indicated on FIG. 5 as circles 36. The effects of the own noise contribution is a common rotation of all constellation points, 30 indicated as a displacement between each xe2x80x9cxxe2x80x9d symbol 34 and its associated circle 36.
This is referred to as the xe2x80x9ccommon phase errorxe2x80x9d, which notably changes from symbol to symbol, and must therefore be recalculated each symbol period TS. The common phase error may also be interpreted as a mean phase deviation during the symbol period TS.
In order for the receiver 32 to process the data symbols in a practical system, a mathematical operation is performed on the complex signal representing each data symbol. Generally this is an FFT. For valid results to be obtained, a particular form of timing synchronization is required in order to align the FFT interval with the received data symbol.
It is therefore a primary object of the invention to provide a highly integrated, low cost apparatus for the reception of digital broadcasts, such as terrestrial digital video broadcasts, which is implemented on a single VLSI chip.
It is another object of the invention to provide an improved method and apparatus for synchronizing a received data symbol with an FFT window in signals transmitted according to COFDM.
It is yet another object of the invention to improve the stability of digital multicarrier receivers in respect of channel estimation.
It is still another object of the invention to improve the automatic frequency control circuitry employed in multicarrier digital receivers.
It is a further object of the invention to improve the automatic sampling rate control circuitry employed in multicarrier digital receivers.
The invention provides a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. The multicarrier signal carries a stream of data symbols having an active interval, and a guard interval in which the guard interval is a replication of a portion of the active interval. In the receiver an analog to digital converter is coupled to a front end amplifier. An I/Q demodulator is provided for recovering in phase and quadrature components from data sampled by the analog to digital converter, and an automatic gain control circuit is coupled to the analog to digital converter. In a low pass filter circuit accepting I and Q data from the I/Q demodulator, the I and Q data are decimated and provided to a resampling circuit. An interpolator in the resampling circuit accepts the decimated I and Q data at a first rate and outputs resampled I and Q data at a second rate. An FFT window synchronization circuit is coupled to the resampling circuit for locating a boundary of the guard interval. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit. Each stage of the FFT processor has a complex coefficient multiplier, and an associated memory with a lookup table defined therein for multiplicands being multiplied in the complex coefficient multiplier. Each multiplicand in the lookup table is unique in value. A monitor circuit responsive to the FFT window synchronization circuit detects a predetermined indication that a boundary between an active symbol and a guard interval has been located.
According to an aspect of the invention the FFT window synchronization circuit has a first delay element accepting currently arriving resampled I and Q data, and outputting delayed resampled I and Q data. A subtracter produces a signal representative of the difference between the currently arriving resampled I and Q data and the delayed resampled I and Q data. In a first circuit the subtracter output signal is converted to a signal having a unipolar magnitude, which is preferably the absolute value of the signal provided by the subtracter. A second delay element stores the output signal of the first circuit, and a third delay element receives the delayed output of the second delay element. In a second circuit a statistical relationship is calculated between data stored in the second delay element and data stored in the third delay element. The output of the FFT window synchronization circuit is representative of the statistical relationship. Preferably the statistical relationship is the F ratio. The FFT processor is capable of operation in a 2K mode and in an 8K mode.
The FFT processor has an address generator for the memory of each stage, which accepts a signal representing the order dependency of a currently required multiplicand, and generates an address of the memory wherein the currently required multiplicand is stored. In a further aspect of the invention each multiplicand is stored in the lookup table in order of its respective order dependency for multiplication by the complex coefficient multiplier, so that the order dependencies of the multiplicands define an incrementation sequence. The address generator has an accumulator for storing a previous address that was generated thereby, a circuit for calculating an incrementation value of the currently required multiplicand responsive to the incrementation sequence, and an adder for adding the incrementation value to the previous address.
In another aspect of the invention there are a plurality of incrementation sequences. The multiplicands are stored in row order, wherein in a first row a first incrementation sequence is 0, in a second row a second incrementation sequence is 1, in a third row first and second break points B1, B2 of a third incrementation sequence are respectively determined by the relationships             B1              M        N              =                            4          N                ⁢                  B1                      M            N                              -                        ∑                      n            =            0                                N            -            1                          ⁢                  4          n                                B2              M        N              =                  ∑                  n          =          0                N            ⁢              4        n            
and in a fourth row a third break point B3 of a third incrementation sequence is determined by the relationship
B3MN=2xc3x974N+2 
wherein MN represents the memory of an Nth stage of the FFT processor.
The receiver provides channel estimation and correction circuitry. Pilot location circuitry receives a transformed digital signal representing a frame from the FFT processor, and identifies the position of pilot carriers therein. The pilot carriers are spaced apart in a carrier spectrum of the transformed digital signal at intervals K and have predetermined magnitudes. The pilot location circuitry has a first circuit for computing an order of carriers in the transformed digital signal, positions of said carriers being calculated modulo K. There are K accumulators coupled to the second circuit for accumulating magnitudes of the carriers in the transformed digital signal, the accumulated magnitudes defining a set. A correlation circuit is provided for correlating K sets of accumulated magnitude values with the predetermined magnitudes. In the correlation a first member having a position calculated modulo K in of each of the K sets is uniquely offset from a start position of the frame.
According to another aspect of the invention the pilot location circuitry also has a bit reversal circuit for reversing the bit order of the transformed digital signal.
According to yet another aspect of the invention amplitudes are used to represent the magnitudes of the carriers. Preferably the magnitudes of the carriers and the predetermined magnitudes are absolute values.
In a further aspect of the invention the correlation circuitry also has a peak tracking circuit for determining the spacing between a first peak and a second peak of the K sets of accumulated magnitudes, wherein the first peak is the maximum magnitude, and the second peak is the second highest magnitude.
The channel estimation and correction circuitry also has an interpolating filter for estimating the channel response between the pilot carriers, and a multiplication circuit for multiplying data carriers output by the FFT processor with a correction coefficient produced by the interpolating filter.
The channel estimation and correction circuitry also has a phase extraction circuit accepting a data stream of phase-uncorrected I and Q data from the FFT processor, and producing a signal representative of the phase angle of the uncorrected data. The phase extraction circuit includes an accumulator for the phase angles of succeeding phase-uncorrected I and Q data.
According to an aspect of the invention the channel estimation and correction circuitry includes an automatic frequency control circuit coupled to the phase extraction circuit, in which a memory stores the accumulated common phase error of a first symbol carried in the phase-uncorrected I and Q data. An accumulator is coupled to the memory and accumulates differences between the common phase error of a plurality of pilot carriers in a second symbol and the common phase error of corresponding pilot carriers in the first symbol. The output of the accumulator is filtered, and coupled to the I/Q demodulator.
According to another aspect of the invention the coupled output of the accumulator of the automatic frequency control circuit is enabled in the I/Q demodulator only during reception of a guard interval therein.
According to yet another aspect of the invention the channel estimation and correction circuitry also has an automatic sampling rate control circuit coupled to the phase extraction circuit, in which a memory stores the individual accumulated phase errors of pilot carriers in a first symbol carried in the phase-uncorrected I and Q data. An accumulator is coupled to the memory and accumulates differences between the phase errors of individual pilot carriers in a second symbol and phase errors of corresponding pilot carriers in the first symbol to define a plurality of accumulated intersymbol carrier phase error differentials. A phase slope is defined by a difference between a first accumulated intersymbol carrier phase differential and a second accumulated intersymbol carrier phase differential. The output of the accumulator is filtered and coupled to the I/Q demodulator.
According to one aspect of the invention the sampling rate control circuit stores a plurality of accumulated intersymbol carrier phase error differentials and computes a line of best fit therebetween.
According to another aspect of the invention the coupled output signal of the accumulator of the automatic sampling rate control circuit is enabled in the resampling circuit only during reception of a guard interval therein.
According to an aspect of the invention a common memory for storing output of the phase extraction circuit is coupled to the automatic frequency control circuit and to the automatic sampling rate control circuit.
According to another aspect of the invention the phase extraction circuit also has a pipelined circuit for iteratively computing the arctangent of an angle of rotation according to the series                     tan                  -          1                    ⁡              (        x        )              =          x      -                        x          3                3            +                        x          5                5            -                        x          7                7            +                        x          9                9            -      …        ⁢      xe2x80x83    ,            "LeftBracketingBar"      x      "RightBracketingBar"         less than     1  
wherein x is a ratio of the phase-uncorrected I and Q data.
The pipelined circuit includes a constant coefficient multiplier, and a multiplexer for selecting one of a plurality of constant coefficients of the series. An output of the multiplexer is connected to an input of the constant coefficient multiplier.
According to still another aspect of the invention the pipelined circuit has a multiplier, a first memory for storing the quantity x2, wherein the first memory is coupled to a first input of the multiplier, and has a second memory for holding an output of the multiplier. A feedback connection is provided between the second memory and a second input of the multiplier. The pipelined circuit also has a third memory for storing the value of the series. Under direction of a control circuit coupled to the third memory, the pipeline circuit computes N terms of the series, and also computes N+1 terms of the series. An averaging circuit is also coupled to the third memory and computes the average of N terms and N+1 terms of the series.
Data transmitted in a pilot carrier of the multicarrier signal is BCH encoded according to a code generator polynomial h(x). A demodulator operative on the BCH encoded data is provided, which includes an iterative pipelined BCH decoding circuit. The BCH decoding circuit is circuit coupled to the demodulator. It forms a Galois Field of the polynomial, and calculates a plurality of syndromes therewith. The BCH decoding circuit includes a plurality of storage registers, each storing a respective one of the syndromes, and a plurality of feedback shift registers, each accepting data from a respective one of the storage registers. The BCH decoding circuit has a plurality of Galois field multipliers. Each of the multipliers is connected in a feedback loop across a respective one of the feedback shift registers and multiplies the output of its associated feedback shift register by an alpha value of the Galois Field. An output Galois field multiplier multiplies the outputs of two of the feedback shift registers.
A logical network forms an error detection circuit connected to the feedback shift registers and to the output Galois field multiplier. The output of the error detection circuit indicates an error in a current bit of data, and a feedback line is enabled by the error detection logic and connected to the storage registers. Using the feedback line, the data output by the feedback shift registers are written back into the storage registers for use in a second iteration.
According to an aspect of the invention the output Galois field multiplier has a first register initially storing a first multiplicand A, a constant coefficient multiplier connected to the first register for multiplication by a value a. An output of the constant coefficient multiplier is connected to the first register to define a first feedback loop, whereby in a kth cycle of clocked operation the first register contains a Galois field product Axcex1k. A second register is provided for storing a second multiplicand B. An AND gate is connected to the second register and to the output of the constant coefficient multiplier. An adder has a first input connected to an output of the AND gate. An accumulator is connected to a second input of the adder, and the Galois field product AB is output by the adder.
The invention provides a method for the estimation of a frequency response of a channel. It is performed by receiving from a channel an analog multicarrier signal that has a plurality of data carriers and scattered pilot carriers. The scattered pilot carriers are spaced apart at an interval N and are transmitted at a power that differs from the transmitted power of the data carriers. The analog multicarrier signal is converted to a digital representation thereof. A Fourier transform is performed on the digital representation of the multicarrier signal to generate a transformed digital signal. The bit order of the transformed digital signal is reversed to generate a bit-order reversed signal. Magnitudes of the carriers in the bit-order reversed signal are cyclically accumulated in N accumulators, amd the accumulated magnitudes are correlated with the power of the scattered pilot carriers. Responsive to the correlation, a synchronizing signal is generated that identifies a carrier position of the multicarrier signal, preferably an active carrier.
According to another aspect of the invention the step of accumulating magnitudes is performed by adding absolute values of a real component of the bit-order reversed signal to respective absolute values of imaginary components thereof to generate sums, and respectively storing the sums in the N accumulators.
According to yet another aspect of the invention the step of correlating the accumulated magnitudes also is performed by identifying a first accumulator having the highest of the N values stored therein, which represents a first carrier position, and by identifying a second accumulator which has the second highest of the N values stored therein, which represents a second carrier position. The interval between the first carrier position and the second carrier position is then determined.
To validate the consistency of the carrier position identification, the position of a carrier of a first symbol in the bit-order reversed signal is compared with a position of a corresponding carrier of a second symbol therein.
Preferably interpolation is performed between pilot carriers to determine correction factors for respective intermediate data carriers disposed therebetween, and respectively adjusting magnitudes of the intermediate data carriers according to the correction factors.
According to an aspect of the invention a mean phase difference is determined between corresponding pilot carriers of successive symbols of the transformed digital signal. A first control signal representing the mean phase difference, is provided to control the frequency of reception of the multicarrier signal. The first control signal is enabled only during reception of a guard interval.
Preferably a line of best fit is determined for the inter-symbol phase differences of multiple carriers to define a phase slope.